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MP2007 3a, 1.3v?6.0v ddr memor y termination regulator MP2007 rev. 0. 9 www.monolithicpower.com 1 7/23/2009 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2009 mps. all rights reserved. the future of analog ic technology descri ption the mp20 07 integrates the ddr me mory termination regulator with the ou tput voltage (vtt) and a buffered vttref outp uts is a half of vref. the vtt-ldo is a 3 a sink/so u rce tracking termination regulator. it is spe c ifically designed for low-cost/low-external component count systems, where space is a premium. the mp20 07 maintains a fast transient response o n ly requiring 20uf (2 x10uf) of ceramic output capa citance. t he mp200 7 supports kelvin sensing f unctions. t h e m p 2 0 0 7 i s a v a i l a b l e i n the 8-pin msop wit h exposed pad ? p a c k a g e and is specified fro m ? 40 o c to 85 o c. features ? vddq voltage range: 1.3v to 6.0 v ? up to 3a integrated sink/source linear regulator with accur a te vref/2 divider reference for ddr ter mination ? requires only 20uf ceramic output capacitance ? drive voltag e range: 4.5 v to 5.5 v ? 1.3v input (vddq) helps reduce total power dissipation ? integrated div i der tracks vref for vtt and vttref ? kelvin sensing (vttsen) ? ? 20mv accuracy for vtt and vttref ? built-in soft-start, uvlo and ocl ? thermal sh utdown appli c ations ? notebook ddr2/3 me mory supply a nd termination voltage in acpi co mpliant ? active termi nation busses ?mp s ? and ?th e fu ture o f a nal og ic t e chno lo gy ? are r e g i ste r ed t r a dem ar ks o f monolithic pow e r sy st em s , inc. typical application c4 0.1uf c7 4.7uf c1 10uf 1206 vtten MP2007dh ref vdr v vttref vttsen vtt vddq ddq 5v 6 1 3 en gnd gnd r3 20 r2 100k 5 7 vttref gnd vtt c6 0.1uf c9 nc c3 10uf 1206 c2 10uf 1206 8 4 2 http://
MP2007 ? 3 a , 1.3v-6.0v input, ddr memory termination regualtor MP2007 rev. 0. 9 www.monolithicpower.com 2 7/23/2009 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2009 mps. all rights reserved. ordering information * for tap e & reel, ad d suf f ix ?z (e.g. MP2007 dh?z); for ro hs compliant pa ckagi ng, add suffix ?lf (e.g. MP2007 dh? l f?z ) package reference ddq vtt gnd vttsen 1 2 3 4 8 7 6 5 vttref en ref vdr v t op view absolute m a xi mum ratings (1) supply voltage v ddq ......................... -0.3v to 6.0v drive voltag e vdrv....... .............. -0 .3v to 6.0v all other pins................ ................ - 0 .3v to 6.0v continuous power dissipation (t a = +25c) (2) ........................................................... 1.56w junction te mperature....................... ........150 o c lead temperature ....... .................... .........260 o c storage temperature .............. -50 o c to +150 o c recommended operating conditions (3) drive voltag e vdrv....... ................ 4. 5v to 5.5v operating temperature .............?40 o c to +85 o c thermal resistance (4) ja jc msop8e ...... .................... ........ 80...... 12... o c/w notes : 1) exceeding these ratings ma y da m age the device. 2) the maximum al low able po wer d i ssipation is a fu nction of the maximum junction temperatu r e t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperatu r e t a . the ma xim u m allow able continuous pow e r dissipation at an y am bient te mperatu r e is calculated b y p d (m ax)=(t j (max)- t a )/ ja . exceed ing the maximu m allow able po wer dissipation w ill cause ex ces s ive die temper atur e, and the r e gulator w ill go into thermal sh utdo w n . intern al thermal shutd o wn circuit r y protects the device from perma ne nt damage. 3) the device is not guarant eed to fu nction outside of its operating conditions. 4) measured on je sd51-7 4 - la y e r b oard. part number* package top marking temperature MP2007dh msop8e 2007d ?40 q c to +85 q c
MP2007 ? 3 a , 1.3v-6.0v input, ddr memory termination regualtor MP2007 rev. 0. 9 www.monolithicpower.com 3 7/23/2009 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2009 mps. all rights reserved. electri c al characteristi cs v drv = 5v, t a = +25 o c, u n less otherw i se noted. parameters symbol test condition min typ max unit vdrv operating voltage vdrv - 4.5 5.0 5.5 v vdrv shut down current idrv_sd vdrv = 5.0 v, vddq=0v - 0.2 1.0 a vdrv op erat ion cu rrent idrv ven_h, vtt = 0.75v 1.3 3 ma vdrv uvlo upper threshold v drvuv+ rising edge - 4.1 4.4 v vdrv uvlo hysteresis vdrvuvhys - - 0.35 - v therm a l trip point tsd - 150 - o c hysteresi s tsdhys - 25 - o c vddq uvlo upper threshold vddquv+ rising edge; hysteresis = 55mv - 0.9 1.3 v 1/2vref ? vtt, vref = 1.8 v, ivtt = 0 to 3 a (sink cur r e n t) ivtt = 0 to ?3 a (source cu rrent) -30 - - - - 30 mv vtt with respec t to 1/2vref dvtt0 1/2vref ? vtt, vref = 1.5 v, ivtt = 0 to 3 a (sink cur r e n t) ivtt = 0 to ?3 a (source cu rrent) -30 - - - - 30 mv ref input resistance ref_r vref = 1.8 v 40 55 75 k source current limit ilimvtsrc - - 3.5 - a sink current limit ilimvtsnk - - 3.5 - a soft ? start source current limit ilimvtss - - 1.0 - a vref=1.8v, vdrv=5v - 9 - maximum soft ? start time ts s v ttmax vref=1.5v, vdrv = 5 v - 7 - us vttref source current ivttr vref = 1.8 v or 1.5 v 15 - - ma 1/2vref ? vttr, vref = 1.8 v, ivttr = 0 ma to 15 ma -18 - 18 mv vttref accurac y referred to 1/2vref dvttr 1/2vref ? vttr, vref = 1.5 v, ivttr = 0 ma to 15 ma -15 - 15 mv ven pin threshold high ven_h - 1.4 - - v ven pin threshold low ven_l - - - 0.5 v ven pin input current iin_ven ven = 5.0 v - - 1.0 a
MP2007 ? 3 a , 1.3v-6.0v input, ddr memory termination regualtor MP2007 rev. 0. 9 www.monolithicpower.com 4 7/23/2009 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2009 mps. all rights reserved. pin functio n s pin # nam e description 1 ddq powe r input for vtt re gula t or. conn ect t o gnd throu gh 10uf ce ra mic ca pa citor. it is normally c o nnec ted to the vddq of ddr memory rail. 2 vtt power output for the vtt ldo. 3 gnd exposed pad the expo sed pad an d gnd pin must be con n e c ted to the same g r o und pla ne. 4 vttsen kelvin sens ed feedba ck sig nal. 5 vdrv chip bias voltage. 6 ref ldo si gnal i nput for generating vddq/2 refere nc e. 7 en vtt regulator enable input. high to enable the chip. 8 vttref buffered output for the system. the receivi ng end of the ddr memory cells needs this signal for their input comparator.
MP2007 ? 3 a , 1.3v-6.0v input, ddr memory termination regualtor MP2007 rev. 0. 9 www.monolithicpower.com 5 7/23/2009 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2009 mps. all rights reserved. typical perfo r manc e characteristics c1=c2=c3=10uf, c4 =c6=0.1uf, c7=4.7uf, v drv =5v, t a =25oc unless otherwise noted. 20us/div source load transient v ddq =v ref =1.8v, v tt =0.9v sink load t ransient v ddq =v ref =2.5v , v tt =0.9v , v sink =1.8v source over current protection v ddq =v ref =2.5v , v tt =1.25v 400us/div 400ms/div 4ms/div power ramp up v ddq =v ref =1.8v, v tt =0.9v startup through down v ddq =v ref =1.8v , v tt =0.9v sink over current protection v ddq =v ref =2.5v , v tt =1.25v ,v sink =2.5v 10ms/div 1s/div v tt 0.5v/div. v ttref 2v/div. i tt 1a/div. v tt 0.5v/div. v ttref 2v/div. v ddq 2v/div v ddq 2v/div v ddq 2v/div i tt 1a/div. v tt 10mv/div. i tt 1a/div. v tt 10mv/div. i tt 1a/div. v tt 1v/div. v ttref 1v/div. i tt 2a/div. v tt 1v/div. v ttref 1v/div. v in 2 v/div. i tt 2a/div. 1. 17 1. 21 1. 25 1. 29 1. 33 1. 37 v ddq =1.8v v ddq =2.5v 0. 67 0. 71 0. 75 0. 79 0. 83 0. 87 v ddq =1.5v v ddq =1.8v 0. 82 0. 86 0. 9 0. 94 0. 98 1. 02 -5 -4 -3 -2 -1 0 1 2 3 4 5 -5 -4 -3 -2 -1 0 1 2 3 4 5 -5 -4 -3 -2 -1 0 1 2 3 4 5 v ddq =2.5v v ddq =1.8v
MP2007 ? 3 a , 1.3v-6.0v input, ddr memory termination regualtor MP2007 rev. 0. 9 www.monolithicpower.com 6 7/23/2009 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2009 mps. all rights reserved. typical performanc e characteristics (continued) c1=c2=c3=10uf, c4 =c6=0.1uf, c7=4.7uf, v drv =5v, t a =25oc unless otherwise noted. . 20us/div 200us/div 20us/div enable on v ddq =v ref =2.5v , v tt =1.25v enable off v ddq =v ref =2.5v , v tt =1.25v 100us/div v tt 0.5 v/div. i tt 2a/div. v tt 0.5 v/div. i tt 2a/div. v tt 10v/div. v en 2v/div. v ddq 2 v/div. i tt 1a/div. v tt 10v/div. v en 2v/div. v ddq 2 v/div. i tt 1a/div. short circuit v ddq =v ref =2.5v , v tt =1.25v short circuit recovery v ddq =v ref =2.5v , v tt =1.25v input supply current vs. temp v ddq =v ref =1.8v , v tt =0.9v shut down input current vs. temp v ddq =v ref =.8v , v tt =0v 0.0 0. 4 0. 8 1. 2 1. 6 2. 0 -40 -10 20 50 80 110 140 i nput c u rrent ( ma ) 0.00 0. 05 0. 10 0. 15 0. 20 0. 25 0. 30 0. 35 0. 40 0. 45 -40 -10 20 50 80 110 140
MP2007 ? 3 a , 1.3v-6.0v input, ddr memory termination regualtor MP2007 rev. 0. 9 www.monolithicpower.com 7 7/23/2009 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2009 mps. all rights reserved. detailed operating descri ption vref vddq vtt vtt regulation & deadband control current limiter current limiter soft-start vttsen vdrv uvlo ddq ddq uv l o vttref vdrv 5v ven gnd re f en ddq vt t sen vt t r ef vt t figure 1?functional block diagram control lo gic the internal control logic is powere d by vdrv. the ic is e nabled whe never both vddq uvl o and vdrv uvlo are p u lled low. v ttref output begins to tr ack vref/2. when the vtten pin is high, the vtt regulator is activated. vttref ou tput the vttref output tracks vref/2 with 2% accuracy. it has source current cap ability of up to 15 ma. vt tref should be bypassed to analo g ground of the device by 1.0 f ceramic capacit or for stable op eration. the vttref is turned o n as long as both vd dq and v d rv a r e hig h er th e uv lo thr e shold. vttref f e at ures a s o ft -s tart a n d tracks vref/2 . output voltages sensing the vtt output voltage is sen s e d across th e vttsen and gnd pins. the vttsen should b e connected t o the vtt regulation p o int, which is usually the vtt local bypass ca pacitor, via a direct sen s e trace. the gnd should be connected v i a a d i rect sense trace t o the groun d of the vtt local bypass capacitor for load. vddq uvl o protectio n for vddq undervoltage lockout (uvlo) protection, t he MP2007 monitors vddq voltage. when the vddq volta ge is lower than uvlo threshold voltage, the v tt regulator is shut off . current pro t ection of vtt active terminator to provide protection f o r the in tern al fets, over current limit( o cl) of 3a i s implemented. the ldo has a consta nt overcurrent limit (ocl) at 3.5 a. th is trip point is reduced to 1.0 a if th e output volta ge drops b e low 1/3 of the targe t voltage.
MP2007 ? 3 a , 1.3v-6.0v input, ddr memory termination regualtor MP2007 rev. 0. 9 www.monolithicpower.com 8 7/23/2009 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2009 mps. all rights reserved. thermal consideration of vtt active terminator the vtt terminator is designed to handle large transient ou tput current s. if large currents ar e required for very long d u ration, the n care shou ld be taken to ensure the maximum junction temperature is not exceeded. the 8-pin msop with exposedpad has a thermal resistance of 50 o c/w (dependent on air flow, and pcb d e sign ). in order to take full a d vantage of the thermal capability o f this package, the exposed pad should be soldered dire ctly onto the pcb gr oun d layer to allow good thermal contact. it is recommend ed that the pcb should have 10 to 15 vias with 0.3mm drill size underneath the exposed thermal pad connecting all the ground layers suppl y voltage undervoltage monitor the ic continuously monitors vdrv. if vdrv is set higher th an its preset threshold a nd vtten i s high too, the ic will start up. thermal shutdow n when the chip jun c tio n temperature exceeds 150 o c , the entire ic is shutd o w n. the ic resumes no rmal operation only afte r the junctio n temperature dropping be low 125 o c .
MP2007 ? 3 a , 1.3v-6.0v input, ddr memory termination regualtor MP2007 rev. 0. 2 www.monolithicpower.com 9 7/23/2009 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2009 mps. all rights reserved. appli c ation information input capacitor depending on the trace impedance from the power supply to the p a rt, transien t increase of source curr ent is supplied mostly b y the charg e from the vddq input capacitor. use a 10 f ( o r more) ceramic capacit or to supply this transie nt charge. provide more i nput capacit ance as more output capacitance is u s ed at vtt. in general, use 1/2 cout for input. output cap acitor for stable o peration, tot a l capacit an ce of the vtt output terminal can be equal or greater than 20 f. attach two 10 f ceramic capacitors in parallel to minimize the effect of esr and esl. if the esr is greater than 10m , i n sert an r-c filter betwee n the output and the v ttsen input to achieve loop stab ility. the r-c filter time constant sh ould be almost the same or slightly lower than the time constant of the output capacitor an d its esr. vdrv capa citor add a cera mic capacit or with a value between 1.0 f and 4.7 f placed close t o t he vdrv pi n, to stabilize 5v from any parasit ic impedance from the supply. thermal design as the MP2007 is a linear regula t or, the vt t current flow in both source and sink direction s generate power dissipation from the device. in the sour ce phase, the potential difference between vddq and vtt times vtt current becomes the power dissipation, psource=(vddq-vtt) x isource in this case, if vddq is conn ected to a n alternative power sup p ly lower than vddq voltage, power loss can be decreased. for the sink phase, vtt voltage is a pplied acro ss the internal ldo reg u lator, and the power dissipat ion psink is: psink=vtt x isink the device does not sin k and source the curren t at the same time and s ource/sink current varie s rapidly with time. the a c tual power dissipat ion t o be consider ed for ther mal design is an avera g e of the above values ov er time. another power consumption is the current used for internal control circuitry from vddq supply. this power needs to be effectively dissipate d from the package. pcb la y o u t guidelines good pcb l a yout design is crit ical t o ensure hig h performance and stable operation of the ddr power controller. the following ite m s must b e considered when preparing pcb layout: 1. all high ? current traces must be kept as sho r t and wide as possible to reduce power loss. high ? current traces are the trace fr om the inpu t voltage terminal to vddq pin, the tr ace from th e vtt output terminal to the load, t he trace from the input ground terminal to the vtt output ground terminal, and th e trace fro m vtt output ground terminal to the gnd pin. power handling and h e a ksinking of high ? current traces can b e improved by also routing the same high ? curren t traces in the other layers by th e same pat h and jo ining the m t ogether with multiple vias. 2. to ensur e the proper function o f the device, separated ground connections sho u ld be used for differen t parts of the application circuit according to their functio n s. the vtt output cap acitor grou nd should be connected t o the gnd pin first with a short trace, it is then co nnected to t he ground plane of gnd. the input capacitor g r ound, the vtt output capacitor ground, the vddq decoupling capacitor g r ound should be connected to the gnd plane. 3. the ther mal pad of the 8-pin m s op package should to be connected t o gnd for b e tter therma l performance. it is reco mmended t o use a pcb with 1 oz or 2oz copper f oil. 4. a separate sense trace should be used to connect the vtt point of regulation, which is usually the local bypass capacitor fo r load, to th e vttsen pin . 5. separat e sense tr ace shou ld be u s ed to connect the vref point of regulation to th e vttref pi n to ensure the accuracy of th e reference voltage to vtt.
MP2007 ? 3 a , 1.3v-6.0v input, ddr memory termination regualtor MP2007 rev. 0. 2 www.monolithicpower.com 10 7/23/2009 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2009 mps. all rights reserved. 6. vddq should be connected to vref inp u t with wide and short tra c e if vddq is used a s t he sourcing su pply for vtt. an input capacitor of at least 10 f should be added close to the vdd q pin and bypassed to gnd if e x t e rnal voltage supply is used as the v tt sourcing supply.
MP2007 ? 3 a , 1.3v-6.0v input, ddr memory termination regualtor notice: t he i n formatio n in this docum ent i s subject to chang e w i t h o u t notice. users sh oul d w a rra nt and gu arante e that third part y int e ll ectu al prop ert y r i g h ts are n o t inf r ing ed u p o n w hen i n tegr atin g mps product s into an y ap p licatio n. mps w i ll not assume a n y le gal res pons ib ili t y for an y sai d app licati ons. MP2007 rev. 0. 9 www.monolithicpower.com 11 7/23/2009 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2009 mps. all rights reserved. package informati o n msop8e (exposed pad) note: 1) contr o l dimension is i n inch es. dimension in bra c ket is in millimeters. 2) packa ge l e ngth does n o t inc l ud e mol d f l ash, prot rusion or gat e burr . 3) packa ge wid t h d o es n o t incl ude in terl ead f l a s h or prot rusion. 4) lead coplan arit y (bott o m of lea ds af ter f o r m ing) sha l l be 0.004 " inch es max. 5) pin 1 iden tif icat ion has h a lf or fu ll circl e opt i on. 6) drawin g meet s jedec mo-187, var i ation a a-t . 7) drawing is not to scale. 0.0 30(0 .75) 0.037(0.95) 0.043(1.10)max 0 . 002(0.05) 0.006(0.15) front view seating plane pin 1 id (note 5) 0.114(2.90) 0.122(3.10) 0.187(4.75) 0.199(5.05) 1 4 5 8 0.010(0.25) 0.014(0.35) 0.0256(0.65)bsc 0.114(2.90) 0.122(3.10) top view 0.004(0.10) 0.008(0.20) side view ga uge pl ane 0.010(0.25) 0. 016(0 . 40) 0.026(0.65) 0 o -6 o recommended land pattern 0.016(0.40) 0.0256(0.65)bsc 0.100(2.54) 0.181(4.60) 0.075(1.90) 0.040(1.00) exposed pad bottom view 0.087(2.20) 0.099(2.50) 0.06 2(1.5 8) 0.074(1.88)

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